This invention relates to memory compression, more particularly, effectively increasing the bandwidth of a memory interface for increasing central processing unit performance by dropping repeated data elements in a data stream, the dropped data elements identified by tagging to cause an error correction code error for later recovery.
Typically, when data is transferred from a central processing unit (CPU) to a memory controller hub (MCH) and then to memory, a bandwidth disparity exists. That is, the bandwidth of the CPU to MCH connection, usually a front side bus (FSB), is higher than the bandwidth of a MCH to memory connection, a memory interface (MI). The FSB often operates at speeds of 500 mega-hertz (MHz.), while the MI often operates at lower speeds such as 100 MHz. or 133 MHz. Since the width of the data bus on both interfaces is usually the same, the effective bandwidth is much higher on the FSB. Everything else being equal, data passing from memory to the CPU would be limited by the MI, not by the FSB. That is, because advancements in CPU speed have outpaced advancements in memory speed, the slower MI speed effects CPU performance.